module top_3_tb;
    reg rst;
    reg clk;
    wire [15:0] data_out;

    // Instantiate the unit under test (UUT)
    top_2 UUT (
        .rst(rst),
        .clk(clk),
        .data_out(data_out)
    );

    initial begin
        // Initialize inputs
        rst = 1;
        clk = 0;

        // Wait for 100 ns
        #20;

        // Release reset
        rst = 0;
     
        #100

        // Finish simulation
        $finish;
    end

    always begin
        #5 clk = ~clk;
    end

    initial begin
        $monitor("clk=%b, rst=%b, data_out=%h", clk, rst, data_out);
    end
endmodule